Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 393)

SystemVerilog Test Programs
SystemVerilog AXI4-Lite Slave BFM Test Program
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 393
April 2014
for(int j = 0; j < addr.size(); j++)
mem_data[j] = do_byte_read(addr[j]);
bfm.set_read_data(read_trans, 0, addr, mem_data);
bfm.execute_read_data_phase(read_trans);
endtask
// Task : process_write
// This method keep receiving write address phase and calls another
method to
// process received transaction.
task process_write;
forever
begin
axi4_transaction write_trans;
write_trans = bfm.create_slave_transaction();
bfm.get_write_addr_phase(write_trans);
fork
begin
automatic axi4_transaction t = write_trans;
handle_write(t);
end
join_none
#0;
end
endtask
// Task : handle_write
// This method receive write data burst or phases for write transaction
// depending upon slave working mode, write data to memory and then send
// response
task automatic handle_write(input axi4_transaction write_trans);
addr_t addr[];
bit [7:0] data[];
bit last;
bfm.get_write_data_phase(write_trans,0,last);
void'(bfm.get_write_addr_data(write_trans, 0, addr, data));
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
set_wr_resp_valid_delay(write_trans);
bfm.execute_write_response_phase(write_trans);
endtask
// Task : handle_write_addr_ready
// This method assert/de-assert the write address channel ready signal.
// Assertion and de-assertion is done based on
m_wr_addr_phase_ready_delay
task automatic handle_write_addr_ready;
bit seen_valid_ready;
int tmp_ready_delay;
axi4_slave_ready_delay_mode_e tmp_mode;