Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 83)

SystemVerilog Slave BFM
get_write_data_cycle()
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 83
April 2014
get_write_data_cycle()
This blocking task waits for a single write data cycle for which the WVALID signal is asserted.
It will block for one ACLK period.
Example
// Wait for a single write data cycle
bfm.get_write_data_cycle();
Prototype task automatic get_write_data_cycle();
Arguments None
Returns None