Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 390)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 390
SystemVerilog Test Programs
SystemVerilog AXI4-Lite Slave BFM Test Program
April 2014
seen_valid_ready = 1'b0;
end
end
endtask
endmodule
SystemVerilog AXI4-Lite Slave BFM Test
Program
The following code example contains a simple slave test program that shows the slave BFM
API being used to communicate with a master and create stimulus. This test program is
discussed further in “
SystemVerilog Tutorials ” on page 115.
// **********************************************************************
//
// Copyright 2007-2014 Mentor Graphics Corporation
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
// THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
// SUBJECT TO LICENSE TERMS.
//
// **********************************************************************
/*
This is a simple example of an AXI4 Slave to demonstrate the
mgc_axi4_slave BFM configured as axi4lite usage.
This is a fairly generic slave which handles almost all write and read
transaction
scenarios from master. It handles write data with address as well as
data after address
both.
This slave code is divided in two parts, one which user might need to
edit to change slave
mode (Transaction/burst or Phase level) and memory handling.
*/
import mgc_axi4_pkg::*;
module slave_test_program #(int AXI4_ADDRESS_WIDTH = 32, int
AXI4_RDATA_WIDTH = 1024, int AXI4_WDATA_WIDTH = 1024, int AXI4_ID_WIDTH =
18, int AXI4_USER_WIDTH = 8, int AXI4_REGION_MAP_SIZE = 16)
(
mgc_axi4_slave bfm
);
typedef bit [((AXI4_ADDRESS_WIDTH) - 1) : 0] addr_t;
// Enum type for slave ready delay mode