Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 403)

VHDL Test Programs
AXI4-Lite VHDL Slave BFM Test Program
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 403
April 2014
begin
set_write_response_valid_delay(2, id, index, path_id, tr_if);
end set_wr_resp_valid_delay;
-- Procedure : set_read_data_valid_delay
-- This will set the ready delay for write data phase
procedure set_read_data_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t) is
variable burst_length : integer;
begin
set_data_valid_delay(2, id, index, tr_if);
end set_read_data_valid_delay;
procedure set_read_data_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t) is
variable burst_length : integer;
begin
set_data_valid_delay(2, id, index, path_id, tr_if);
end set_read_data_valid_delay;
begin
-- To create pipelining in VHDL there are multiple channel path in each
API.
-- So each process will choose separate path to interact with BFM.
-- process_write : write address phase through path 0
-- This process keep receiving write address phase and push the
transaction into queue through
-- push_transaction_id API.
process
variable write_trans : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, axi4_tr_if_0(index));
wait_on(AXI4_CLOCK_POSEDGE, index, axi4_tr_if_0(index));
loop
create_slave_transaction(write_trans, index, axi4_tr_if_0(index));
get_write_addr_phase(write_trans, index, axi4_tr_if_0(index));
push_transaction_id(write_trans, AXI4_QUEUE_ID_0, index,
axi4_tr_if_0(index));
end loop;
wait;
end process;
-- handle_write : write data phase through path 1
-- This method receive write data phase for write transaction
process
variable write_trans: integer;
variable byte_length : integer;
variable addr : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);
variable data : std_logic_vector(7 downto 0);
variable last : integer := 0;
begin
loop
pop_transaction_id(write_trans, AXI4_QUEUE_ID_0, index, AXI4_PATH_1,
axi4_tr_if_1(index));
get_write_data_phase(write_trans, 0, last, index, AXI4_PATH_1,
axi4_tr_if_1(index));