Fluke Biomedical 945A - Manual (Page 47)

Universal Digital Ratemeter (UDR), Model 946A-200
The Model 946A-200 UDR is composed of five (5) circuit board assemblies mounted within the unit.
These circuit boards provide input/output, display, power, and control for the UDR. Each circuit board is
described in detail in the following sections and accompanied by a block diagram where applicable.
Schematic diagrams are located in Appendix B.
Main Circuit Board
The main circuit board contains the microprocessor, memory, standard analog outputs, and control
circuitry. The following paragraphs explain the operation of the circuits in detail. Figure 4-2 is a block
diagram of the main circuit board.
Microprocessor
The 6802 /6808 (U15) is a monolithic 8 bit microprocessor with 16 bit memory addressing. The 6802 /
6808 contains a crystal controlled internal clock oscillator and driver circuitry.
A 4 MHz crystal is utilized with the internal clock circuitry to obtain 1 MHz operation. The (E) enable pin
on the MPU supplies the clock for both the MPU and the rest of the system. Figure 4-3 is a typical timing
diagram for write and read cycles.
The read/write output signals the memory / peripherals that the MPU is in a read (high) state or a write
(low) state. The normal standby state is read (high).
The valid memory address (VMA) output indicates to peripheral and memory devices that there is a valid
address on the address bus.
The address bus outputs (A0 - A15) provide for addressing of external devices.
The data bus (D0 - D7) is bi-directional and is used for transferring data between the MPU and
memory/peripheral devices. The data bus will be in the output mode for a write cycle and in the input
mode for a read cycle.
The Interrupt Request Input (IRQ), when low, requests that an interrupt sequence be generated within the
MPU. The processor will wait until it completes the current instruction that is being executed before it
recognizes the request. Various internal registers are stored on the stack before a branch to the interrupt
vector is carried out. When the interrupt routine has completed, the registers are restored and the MPU
continues to execute the program. The IRQ input is not utilized on the main circuit board, however, it is
provided to the external bus connector to be used by IRQ generating devices located on the option
boards.
The reset input (active low) is used to restart the MPU from a power down condition, (restart from a
power failure or an initial start-up). A manual detector MPU reset is also provided via SW2, on the 977-
210-10 board. A low to high transition on this input signals the MPU to begin the restart sequence.
The non-maskable interrupt (NMI) input, upon detection of a low-going edge, requests that a
nonmaskable interrupt sequence is generated within the MPU. As with the interrupt request signal, the
processor will complete the current instruction being executed before it recognizes the NMI signal.
Various internal registers are stored on the stack before a branch to the NMI vector occurs. Upon
completion of the NMI routine, the internal registers are restored and program execution continues.
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