Nevion FSR-HD - Manual (Page 30)

FRS-HD Rev. G
nevion.com | 30
Note 2: The resolution of the lvl control
is 0.5dB but the card will perform correct
rounding to nearest legal value and report
the resulting setting. Legal input range is
[-957cBu, 247cBu], representing the
range [-95.5dBu, 24.5dBu].
uart 0 - tx The embedded data link, selectable by
cho 13. No control possible, the word tx
indicates that this is a transceiver only.
Uart info reports link status: los (loss of
signal), raw, or the speed of the
embedded link (example: 115200/8/n/1).
6.4.3 Commands intended for debug/lab use only
Block Blk
#
Commands example Response Control
spi - on | off spi on
spi off spi off used to isolate the uC from the
SPI lines during programming of the
flash by external programmer. spi on
must be issued in order to re-enable
normal card operation with the uC as the
SPI master.
spir - <address> spir 0x0004 Read a single word (or byte) from a SPI
registers. Addressing is 16b and most
significant nibble determines which chip.
These are the address ranges:
0x0000 – 0x0fff : audio DAC
0x1000 – 0x1fff : FPGA
0x2000 – 0x2fff : flash
0x3000 – 0x3fff : deserializer
0x4000 – 0x4fff : serializer
0x5000 – 0x5fff : shift register (for
LEDs)
0x6000 – 0x7fff : Not in use on this
module.
spiw - <address> <data> spiw 0x0004 0x2c With the same address ranges as for spir
above, this command allows the user to
modify SPI registers.
thebug - - thebug A collection of debug information that is
presented in a Gyda block-like format.
First line tells which image is currently
loaded. Second line contains the filename
and version of the uC software, including
the AVR controller it was compiled for.
The third line contains the SW flags in
uC, the number of times the watchdog
timr has kicked in, readout of dip-
switches, input select for deserializer,
SDOn on/off, slew rates, and status for
the video changeovers.
The next two lines contain raster
information from the deserializer and
serializer respectively, while the last two
lines contain sample values for mlines
and VCXO.