Verilink SCC 2130 (880-503282-001) Product Manual - Manual (Page 17)

Quick Set-Up
Verilink SCC 2130 User Manual 2-3
NOTE: Whenever the word UPDATE appears in the command line
prompt, it indicates that some information has changed since
the screen was last refreshed. To refresh the screen with
current information, simply press E NTER .
Figure 2-3 SCC 2130 Configuration Menu
The factory default values for the SCC 2130 are shown. The
network interface, shown on the right at the top, is set for ESF
framing and B8ZS line coding.
The DTE interface, shown at top left, is set for 64K per DS0 and LOS
(Loss Of Signal) detection is off.
1. Type “G” and press E NTER , the prompt for LOS lead selection
appears: los lead (1) dtr (2) rts (3) none > los lead (1) dtr (2) rts (3) none > los lead (1) dtr (2) rts (3) none > los lead (1) dtr (2) rts (3) none > type “2” and press
E NTER to use Request To Send. This means that the IDCSU will
indicate an alarm condition whenever it does not see RTS held
high by the router. The EQPT LED begins blinking in a red, red,
green pattern because the router is not connected yet.
2. By default, all 24 timeslots of the T1 are assigned to the data
port. For this example, only the first twelve are used. Type “D”
and press E
NTER . The prompt used to select timeslots appears,
ENTER CHANNELS: ENTER CHANNELS: ENTER CHANNELS: ENTER CHANNELS:. Type “1-12” and press E
NTER .
IDCSU CONFIGURATION FW/HW Rev..1.25/0.8 IDCSU CONFIGURATION FW/HW Rev..1.25/0.8 IDCSU CONFIGURATION FW/HW Rev..1.25/0.8 IDCSU CONFIGURATION FW/HW Rev..1.25/0.8
|-----------------------|
|-----------------------| |-----------------------| |-----------------------|
-------<< dte <<-------| T) alm thld DEF |-------<< net <<-------
-------<< dte <<-------| T) alm thld DEF |-------<< net <<------- -------<< dte <<-------| T) alm thld DEF |-------<< net <<------- -------<< dte <<-------| T) alm thld DEF |-------<< net <<-------
M) mode 64K | | W) framing ESF
M) mode 64K | | W) framing ESF M) mode 64K | | W) framing ESF M) mode 64K | | W) framing ESF
N) scramble OFF | | F) format B8ZS
N) scramble OFF | | F) format B8ZS N) scramble OFF | | F) format B8ZS N) scramble OFF | | F) format B8ZS
C) clocking ST | | J) jitt buf 40 BITS
C) clocking ST | | J) jitt buf 40 BITS C) clocking ST | | J) jitt buf 40 BITS C) clocking ST | | J) jitt buf 40 BITS
G) los lead NONE | | L) lbo 0 DB
G) los lead NONE | | L) lbo 0 DB G) los lead NONE | | L) lbo 0 DB G) los lead NONE | | L) lbo 0 DB
------->> dte >>-------| I) idle code ONES |------->> net >>-------
------->> dte >>-------| I) idle code ONES |------->> net >>------- ------->> dte >>-------| I) idle code ONES |------->> net >>------- ------->> dte >>-------| I) idle code ONES |------->> net >>-------
|-----------------------| Z) density 12%+80z
|-----------------------| Z) density 12%+80z |-----------------------| Z) density 12%+80z |-----------------------| Z) density 12%+80z
lead toggles: DTR) DSR) RTS) CTS) DCD) lead toggles: DTR) DSR) RTS) CTS) DCD) lead toggles: DTR) DSR) RTS) CTS) DCD) lead toggles: DTR) DSR) RTS) CTS) DCD)
forced leads: Y N N N N
forced leads: Y N N N N forced leads: Y N N N N forced leads: Y N N N N
D) select DS-0 (1-24) B) timing NET D) select DS-0 (1-24) B) timing NET D) select DS-0 (1-24) B) timing NET D) select DS-0 (1-24) B) timing NET
01 02 03 04 05 06 07 08 09 10 11 12 P) prm NONE
01 02 03 04 05 06 07 08 09 10 11 12 P) prm NONE 01 02 03 04 05 06 07 08 09 10 11 12 P) prm NONE 01 02 03 04 05 06 07 08 09 10 11 12 P) prm NONE
13 14 15 16 17 18 19 20 21 22 23 24 C1-C7) canned config
13 14 15 16 17 18 19 20 21 22 23 24 C1-C7) canned config 13 14 15 16 17 18 19 20 21 22 23 24 C1-C7) canned config 13 14 15 16 17 18 19 20 21 22 23 24 C1-C7) canned config
O) poll far end (ON)
O) poll far end (ON) O) poll far end (ON) O) poll far end (ON)
A) Alarm ENABLE
A) Alarm ENABLE A) Alarm ENABLE A) Alarm ENABLE
V) Data Invert No
V) Data Invert No V) Data Invert No V) Data Invert No
[1,1] NEAR IDCSU 2130 > [1,1] NEAR IDCSU 2130 > [1,1] NEAR IDCSU 2130 > [1,1] NEAR IDCSU 2130 >