Document Outline

• LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller
  • Preface
  • Contents
  • Chapter1 Introduction
    • 1.1 General Description
      • Figure1.1 Typical LSI53C1020 Board Application
      • Figure1.2 Typical LSI53C1020 System Application
    • 1.2 Benefits of the Fusion-MPT Architecture
    • 1.3 Benefits of PCI-X
    • 1.4 Benefits of Ultra320 SCSI
    • 1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation)
    • 1.6 Benefits of LVDlink Technology
    • 1.7 Benefits of TolerANT® Technology
    • 1.8 Summary of LSI53C1020 Features
      • 1.8.1 SCSI Performance
      • 1.8.2 PCI Performance
      • 1.8.3 Integration
      • 1.8.4 Flexibility
      • 1.8.5 Reliability
      • 1.8.6 Testability
  • Chapter2 Functional Description
    • 2.1 Block Diagram Description
      • Figure2.1 LSI53C1020 Block Diagram
      • 2.1.1 Host Interface Module Description
      • 2.1.2 SCSI Channel Module Description
    • 2.2 Fusion-MPT Architecture Overview
    • 2.3 PCI Functional Description
      • 2.3.1 PCI Addressing
      • 2.3.2 PCI Commands and Functions
        • Table2.1 PCI/PCI-X Bus Commands and Encodings
      • 2.3.3 PCI Arbitration
      • 2.3.4 PCI Cache Mode
      • 2.3.5 PCI Interrupts
      • 2.3.6 Power Management
        • Table2.2 Power States
    • 2.4 Ultra320 SCSI Functional Description
      • 2.4.1 Ultra320 SCSI Features
        • Figure2.2 Paced Transfer Example
        • Figure2.3 Example of Precompensation
      • 2.4.2 SCSI Bus Interface
    • 2.5 External Memory Interfaces
      • 2.5.1 Flash ROM Interface
        • Table2.3 Flash ROM Size Programming
        • Figure2.4 Flash ROM Block Diagram
        • Table2.4 Flash Signature Value
      • 2.5.2 NVSRAM Interface
        • Figure2.5 NVSRAM Diagram
    • 2.6 Serial EEPROM Interface
      • Table2.5 PCI Configuration Record in Serial EEPROM
    • 2.7 Zero Channel RAID
      • Figure2.6 ZCR Circuit Diagram for the LSI53C1020 and LSI53C1000R
    • 2.8 Multi-ICE Test Interface
      • Table2.6 20-Pin Multi-ICE Header Pinout
  • Chapter3 Signal Description
    • 3.1 Signal Organization
      • Figure3.1 LSI53C1020/1020A Functional Signal Grouping
    • 3.2 PCI Bus Interface Signals
      • 3.2.1 PCI System Signals
        • Table3.1 PCI System Signals
      • 3.2.2 PCI Address and Data Signals
        • Table3.2 PCI Address and Data Signals
      • 3.2.3 PCI Interface Control Signals
        • Table3.3 PCI Interface Control Signals
      • 3.2.4 PCI Arbitration Signals
        • Table3.4 PCI Arbitration Signals
      • 3.2.5 PCI Error Reporting Signals
        • Table3.5 PCI Error Reporting Signals
      • 3.2.6 PCI Interrupt Signals
        • Table3.6 PCI Interrupt Signal
    • 3.3 PCI-Related Signals
      • Table3.7 PCI-Related Signals
    • 3.4 SCSI Interface Signals
      • Table3.8 SCSI Bus Clock Signal
      • Table3.9 SCSI Channel Interface Signals
      • Table3.10 SCSI Channel Control Signals
    • 3.5 Memory Interface
      • Table3.11 Flash ROM/NVSRAM Interface Signals
      • Table3.12 Serial EEPROM Interface Signals
    • 3.6 Zero Channel RAID (ZCR) Interface
      • Table3.13 ZCR Configuration Signals
    • 3.7 Test Interface
      • Table3.14 JTAG, ICE, and Debug Signals
      • Table3.15 LSI Logic Test Signals
    • 3.8 GPIO and LED Signals
      • Table3.16 GPIO and LED Signals
    • 3.9 Power and Ground Pins
      • Table3.17 Power and Ground Pins
      • Table3.18 No Connect Pins
    • 3.10 Power-On Sense Pins Description
      • Table3.19 MAD Power-On Sense Pin Options
      • Table3.20 Flash ROM Size Programming
    • 3.11 Internal Pull-Ups and Pull-Downs
      • Table3.21 Pull-Up and Pull-Down Signal Conditions
  • Chapter4 PCI Host Register Description
    • 4.1 PCI Configuration Space Register Descriptions
      • Table4.1 LSI53C1020 PCI Configuration Space Address Map
      • Vendor ID
      • Device ID
      • Command
      • Status
      • Revision ID
      • Class Code
      • Cache Line Size
      • Latency Timer
      • Header Type
      • I/O Base Address
      • Memory [0] Low
      • Memory [0] High
      • Memory [1] Low
      • Memory [1] High
      • Subsystem Vendor ID
      • Subsystem ID
        • Table4.2 Subsystem ID Register Download Conditions and Values
      • Expansion ROM Base Address
      • Capabilities Pointer
      • Interrupt Line
      • Interrupt Pin
      • Minimum Grant
      • Maximum Latency
      • Power Management Capability ID
      • Power Management Next Pointer
      • Power Management Capabilities
      • Power Management Control/Status
      • Power Management Bridge Support Extensions
      • Power Management Data
      • MSI Capability ID
      • MSI Next Pointer
      • Message Control
      • Message Address
      • Message Upper Address
      • Message Data
      • PCI-X Capability ID
      • PCI-X Next Pointer
      • PCI-X Command
      • PCI-X Status
    • 4.2 I/O Space and Memory Space Register Descriptions
      • Table4.3 PCI I/O Space Address Map
      • Table4.4 PCI Memory [0] Address Map
      • Table4.5 PCI Memory [1] Address Map
      • System Doorbell
      • Write Sequence
      • Host Diagnostic
      • Test Base Address
      • Diagnostic Read/Write Data
      • Diagnostic Read/Write Address
      • Host Interrupt Status
      • Host Interrupt Mask
      • Request Queue
      • Reply Queue
  • Chapter5 Specifications
    • 5.1 DC Characteristics
      • Table5.1 Absolute Maximum Stress Ratings
      • Table5.2 Operating Conditions
      • Table5.3 LVD Driver SCSI Signals – SACK±, SATN±, SBSY±, SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±,...
      • Figure5.1 LVD Driver
      • Table5.4 LVD Receiver SCSI Signals – SACK±, SATN±, SBSY±, SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG...
      • Figure5.2 LVD Receiver
      • Table5.5 DIFFSENS SCSI Signal
      • Table5.6 Input Capacitance
      • Table5.7 8 mA Bidirectional Signals – GPIO[7:0], MAD[15:0], MADP[1:0], SerialDATA
      • Table5.8 8 mA PCI Bidirectional Signals – ACK64/, AD[63:0], C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, ...
      • Table5.9 Input Signals – CLK, DIS_PCI_FSN/, DIS_SCSI_FSN/, GNT/, IDDTN, IDSEL, IOPD_GNT, BZRESET...
      • Table5.10 8 mA Output Signals – ALT_INTA/, RAMWE[1:0]/, FLSHALE[1:0]/, FLSHCE/, INTA/, RAMOE/, R...
      • Table5.11 12 mA Output Signals – A_LED/, HB_LED/
    • 5.2 TolerANT Technology Electrical Characteristics
      • Table5.12 TolerANT Technology Electrical Characteristics for SE SCSI Signals
      • Figure5.3 Rise and Fall Time Test Condition
      • Figure5.4 SCSI Input Filtering
    • 5.3 AC Characteristics
      • Table5.13 External Clock
      • Figure5.5 External Clock
      • Table5.14 Reset Input
      • Figure5.6 Reset Input
      • Table5.15 Interrupt Output
      • Figure5.7 Interrupt Output
    • 5.4 External Memory Timing Diagrams
      • 5.4.1 NVSRAM Timing
        • Table5.16 NVSRAM Read Cycle Timing
        • Figure5.8 NVSRAM Read Cycle
        • Table5.17 NVSRAM Write Cycle
        • Figure5.9 NVSRAM Write Cycle
      • 5.4.2 Flash ROM Timing
        • Table5.18 Flash ROM Read Cycle Timing
        • Figure5.10 Flash ROM Read Cycle
        • Table5.19 Flash ROM Write Cycle
        • Figure5.11 Flash ROM Write Cycle
    • 5.5 Pinout Information and Mechanical Drawings
      • Figure5.12 LSI53C1020 456-Pin BGA Top View
      • Table5.20 LSI53C1020 456-Pin Pinout by Signal Name
      • Table5.21 LSI53C1020 456-Pin Pinout by BGA Position
      • Figure5.13 LSI53C1020A 384-Pin BGA, Top View
      • Table5.22 LSI53C1020A 384-Pin Pinout by Signal Name
      • Table5.23 LSI53C1020A 384-Pin Pinout by BGA Position
      • Figure5.14 456-Pin EPBGA (KY) Mechanical Drawing
      • Figure5.15 384-Ball Count EPBGA (HT) Mechanical Drawing (Sheet 1 of 2)
      • Figure5.16 448-Ball Count EPBGA (5B) Mechanical Drawing (Sheet 1 of 2)
  • AppendixA Register Summary
    • TableA.24 LSI53C1020 PCI Registers
    • TableA.25 LSI53C1020 PCI I/O Space Registers
    • TableA.26 LSI53C1020 PCI Memory [0] Registers
  • Index
  • Customer Feedback