FUJITSU MHT2060BH User Manual
Page 166
Interface
5-92 C141-E203-01EN
*13 WORD 78
Bit15-5: Reserved
Bit 4:
'1'= Supports the in-order data delivery.
Bit 3:
'1'= Supports the Power Management initiation from the device to
the host system.
Bit 2:
'1' = Supports the DMA Setup FIS Auto-Activate optimization.
Bit 1:
'1' = Supports the non-zero buffer offset in the DMA Setup FIS.
Bit 0:
Reserved
*14 WORD 79
Bit15-5: Reserved
Bit 4:
'1' = Enables the in-order data delivery.
Bit 3:
'1' = Enables the Power Management initiation function from Bit 2:
'1' = Enables the Auto-Activate optimization function in the DMA
Setup FIS.
Bit 1:
'1' = Enables the non-zero buffer offset function in the DMA Setup
FIS.
Bit 0:
Reserved
*15 WORD 80
Bit 15-8:
Reserved
Bit 7:
'1' = ATA/ATAPI-7 supported
Bit 6:
'1' = ATA/ATAPI-6 supported
Bit 5:
'1' = ATA/ATAPI-5 supported
Bit 4:
'1' = ATA/ATAPI-4 supported
Bit 3:
'1' = ATA-3 supported
Bit 2:
'1' = ATA-2 supported
Bit 1-0:
Undefined
*16 WORD 82
Bit 15:
Undefined
Bit 14:
'1' = Supports the NOP command.
Bit 13:
'1' = Supports the READ BUFFER command.
Bit 12:
'1' = Supports the WRITE BUFFER command.
Bit 11:
Undefined