Seagate Fibre Channel Interface User Manual
Page 254
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Fibre Channel Interface Manual, Rev. D
DLM (Disable Loop Master)
1
Indicates that a target attached to an FC-AL-2 loop shall not participate in loop master arbitration and shall not
become loop master. The target shall only repeat LISM frames it receives.
0
The target may participate in loop master arbitration in the normal manner and, if successful, may become loop
master during the loop initialization process. Targets not attached to an arbitrated loop shall ignore the DLM bit.
DSA (Disable Soft Address)
1
The target does not select a soft address if there is a conflict for the Select_ID address available in the SCA connec-
tor during loop initialization. If there is a Select_ID address conflict, the target enters the non-participation state. If
the target detects loop initialization while in the non-participation state, the target again attempts to get the Select_ID
address.
0
The target attempts to obtain a soft address during loop initialization if the Select_ID address is not available or if the
Select_ID address indicates the use of a soft address (7Fh).
If ESI activity is underway when the request for the hard address is received, the drive shall use the last known value of the
hard address before the current ESI activity started. For more information on ESI, refer to Section 10.5.
DTFD (Disable Target Fabric Discovery)
1
The target attached by an FC-AL loop will not recognize the presence of a fabric loop port (FL_Port) on the loop.
The target will only perform the private loop functions defined for FC-PLDA targets.
0
The target attached by an FC-AL loop will discover the FL_Port if present on the loop and will perform the public
loop functions defined for FC-FLA targets. Targets attached to an N_Port or to an F_Port will ignore this bit.
DTIPE (Disable Target Initiated Port Enable)
1
The target waits for an initiator to send the Loop Port Enable primitive before inserting itself into the loop. The target
uses the Select_ID address available in the SCA connector to determine if primitives are addressed to it.
Note.
Do not set the PLPB bit to one (1) and the DTIPE bit to one (1) at the same time as this is an illegal bit combina-
tion. When an illegal bit combination is sent by the application client, the device server returns Check Condition
status and sets the sense key to Illegal Request with the additional sense code set to Invalid Field in the Parame-
ter List.
0
After completing self test, the target enables the port in the loop without waiting for a Loop Port Enable primitive.
DTOLI (Disable Target Originated Loop Initialization)
1
The target does not originate the initializing LIP following insertion into the loop. The target responds to an Initializ-
ing LIP when it is received. The target originates the Loop Failure LIP if it detects loop failure at its input. The target
originates the Initializing LIP when the loop failure is corrected.
0
After completing self test, the target originates the Initializing LIP when it enables a port in a loop.
Page Code
19h
Fibre Channel Interface Control page code.
Page Length
06h
The length of the Fibre Channel Interface Control page (in bytes). If the allocation length is too small to transfer all of
the page, the page length is not adjusted to reflect the truncation.
PS (Parameter Savable)
This bit is only used with the Mode Sense command. This bit is not used with the Mode Select command.
1
The drive is capable of saving the page in a nonvolatile vendor-specific location.
PLPB (Prevent Loop Port Bypass)
1
The target ignores any Loop Port Bypass (LPB) and Loop Port Enable (LPE) primitive sequences. The loop port
remains enabled.
Note.
Do not set the PLPB bit to one (1) and the DTIPE bit to one (1) at the same time as this is an illegal bit combina-
tion. When an illegal bit combination is sent by the application client, the device server returns Check Condition
status and sets the sense key to Illegal Request with the additional sense code set to Invalid Field in the Parame-
ter List.
0
The target allows the Loop Port Bypass and Port Bypass Enable primitive sequences to control the port bypass cir-
cuit.