NEC uPD75P3116 User Manual
Page 34
µ
PD75P3116
34
Data Sheet U11369EJ3V0DS
Subsystem Clock Oscillator Characteristics (T
A
= –40 to +85˚C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended Constant
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Crystal
Oscillation
32
32.768
35
kHz
resonator
frequency (f
XT
)
Note 1
Oscillation
V
DD
= 4.5 to 5.5 V
1.0
2
s
stabilization time
Note 2
V
DD
= 1.8 to 5.5 V
10
External
XT1 input frequency
32
100
kHz
clock
(f
XT
)
Note 1
XT1 input high-/low-level
5
15
µ
s
width (t
XTH
, t
XTL
)
Notes 1.
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2.
The oscillation stabilization time is necessary for oscillation to stabilize after applying V
DD
.
Caution
When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as V
DD
.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption
current, and is more liable to misoperation by noise than the main system clock oscillator. Special
care should therefore be taken regarding the wiring method when the subsystem clock is used.
XT2
XT1
C4
V
DD
C3
R
XT1
XT2