NEC uPD75P3116 User Manual
Page 38
µµµµµ
PD75P3116
38
Data Sheet U11369EJ3V0DS
Serial Transfer Operation
2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (T
A
= –40 to +85˚C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY1
V
DD
= 2.7 to 5.5 V
1300
ns
V
DD
= 1.8 to 5.5 V
3800
ns
SCK high-/low-level
t
KL1
, t
KH1
V
DD
= 2.7 to 5.5 V
t
KCY1
/2–50
ns
width
V
DD
= 1.8 to 5.5 V
t
KCY1
/2–150
ns
SI
Note 1
setup time
t
SIK1
V
DD
= 2.7 to 5.5 V
150
ns
(to SCK
↑
)
V
DD
= 1.8 to 5.5 V
500
ns
SI
Note 1
hold time
t
KSI1
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
↑
)
V
DD
= 1.8 to 5.5 V
600
ns
SO
Note 1
output delay
t
KSO1
R
L
= 1 k
Ω
,
V
DD
= 2.7 to 5.5 V
0
250
ns
time from SCK
↓
C
L
= 100 pF
Note 2
V
DD
= 1.8 to 5.5 V
0
1000
ns
Notes 1.
In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead.
2.
R
L
and C
L
are the load resistance and load capacitance of the SO output lines, respectively.
2-wire and 3-wire serial I/O mode (SCK...External clock input): (T
A
= –40 to +85˚C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY2
V
DD
= 2.7 to 5.5 V
800
ns
V
DD
= 1.8 to 5.5 V
3200
ns
SCK high-/low-level
t
KL2
,
t
KH2
V
DD
= 2.7 to 5.5 V
400
ns
width
V
DD
= 1.8 to 5.5 V
1600
ns
SI
Note 1
setup time
t
SIK2
V
DD
= 2.7 to 5.5 V
100
ns
(to SCK
↑
)
V
DD
= 1.8 to 5.5 V
150
ns
SI
Note 1
hold time
t
KSI2
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
↑
)
V
DD
= 1.8 to 5.5 V
600
ns
SO
Note 1
output delay
t
KSO2
R
L
= 1 k
Ω
,
V
DD
= 2.7 to 5.5 V
0
300
ns
time from SCK
↓
C
L
= 100 pF
Note 2
V
DD
= 1.8 to 5.5 V
0
1000
ns
Notes 1.
In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead.
2.
R
L
and C
L
are the load resistance and load capacitance of the SO output lines, respectively.