NEC uPD75P3116 - Manual (Page 6)

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PD75P3116
6 Data Sheet U11369EJ3V0DS
2. BLOCK DIAGRAM
P20 to P23
P00 to P03
S0 to S15 16
4
4
4
4
4
4
4
4
COM0 to COM3 4
BIAS f LCD
V PP V DD RESET Vss
CPU clock Φ
Standby
control
X2 X1 XT2 XT1
System clock
generator
Main Sub
Clock
divider
Clock
output
control
fx/2 N
PCL/PTO2/P22
General-
purpose
register
Data
memory
(RAM)
512 × 4 bits
Bank
SBS
SP (8)
CY
ALU
Program
counter (14)
Program
memory
(PROM)
16384 × 8 bits
Decode
and
control
P10 to P13
P30/MD0 to
P33/MD3
P50/D4 to
P53/D7
P60/D0 to
P63/D3
P80 to P83
Port 0
Port 1
Port 2
Port 3
Port 5
Port 6
Port 8
Port 9 P90 to P93
LCD
controller/driver
4
S16/P93 to
S19/P90
4
S20/P83 to
S23/P80
V LC0
V LC1
V LC2
SYNC/P31
LCDCL/P30
Clocked
serial
interface SI/SB1/P03
INTCSI
Interrupt
control
INT0/P10
SO/SB0/P02
SCK/P01
TOUT0
INT1/P11
INT4/P00
INT2/P12/TI1/TI2
P60/KR0 to
P63/KR3
Bit sequential
buffer (16)
4
INT1
8-bit
timer/event
counter #1
8-bit
timer/event
counter #2
Cascaded
16-bit
timer/
event
counter
INTT2
INTT1
TI1/TI2/
P12/INT2
PTO1/P21
TOUT0
PTO2/
PCL/P22
INTT0 TOUT0
8-bit
timer/event
counter #0
TI0/P13
PTO0/P20
Basic
interval
timer/
watchdog
timer
INTBT
BUZ/P23
Watch
timer
INTW f LCD