NEC uPD75P3116 - Manual (Page 35)

µµµµµ
PD75P3116
35 Data Sheet U11369EJ3V0DS
DC Characteristics (T
A
= –40 to +85˚C, V
DD
= 1.8 to 5.5 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Output current, low I
OL
Per pin 15 mA
Total of all pins 150 mA
Input voltage, high V IH1 Ports 2, 3, 8, and 9 2.7 ≤ V DD
≤ 5.5 V 0.7V DD V DD V
1.8 ≤ V
DD
< 2.7 V 0.9V
DD
V
DD
V
V IH2 Ports 0, 1, 6, RESET 2.7 ≤ V DD
≤ 5.5 V 0.8V DD V DD V
1.8 ≤ V DD < 2.7 V 0.9V DD V DD V
V
IH3
Port 5 2.7 ≤ V
DD
≤ 5.5 V 0.7V
DD
13 V
(N-ch open-drain) 1.8 ≤ V DD < 2.7 V 0.9V DD 13 V
V IH4 X1, XT1 V DD – 0.1 V DD V
Input voltage, low V
IL1
Ports 2, 3, 5, 8, and 9 2.7 ≤ V
DD
≤ 5.5 V 0 0.3V
DD
V
1.8 ≤ V DD < 2.7 V 0 0.1V DD V
V IL2 Ports 0, 1, 6, RESET 2.7 ≤ V DD
≤ 5.5 V 0 0.2V DD V
1.8 ≤ V
DD
< 2.7 V 0 0.1V
DD
V
V IL3 X1, XT1 0 0.1 V
Output voltage, high V OH SCK, SO, Ports 2, 3, 6, 8, and 9 I OH = –1.0 mA V DD – 0.5 V
Output voltage, low V
OL1
SCK, SO, Ports 2, 3, 5, 6, 8, and 9 I
OL
= 15 mA, 0.2 2.0 V
V DD = 4.5 to 5.5 V
I OL = 1.6 mA 0.4 V
V
OL2
SB0, SB1 When N-ch open-drain 0.2V
DD
V
pull-up resistor ≥ 1 k Ω
Input leakage I LIH1 V IN = V DD Pins other than X1, XT1 3
µ
A
current, high I
LIH2
X1, XT1 20 µ A
I LIH3 V IN = 13 V Port 5 (N-ch open-drain) 20 µ A
Input leakage I LIL1 V IN = 0 V Pins other than X1, XT1, and Port 5 –3 µ A
current, low I
LIL2
X1, XT1 –20 µ A
I LIL3 Port 5 (N-ch open-drain) –3 µ A
When another instruction than input
instruction is executed
V DD = 1.8 to 5.5 V –30 µ A
V DD = 5.0 V –10 –27 µ A
V
DD
= 3.0 V –3 –8 µ A
Output leakage I LOH1 V OUT = V DD SCK, SO/SB0, SB1, Ports 2, 3, 6, 8, and 9 3 µ A
current, high I LOH2 V OUT = 13 V Port 5 (N-ch open-drain) 20
µ
A
Output leakage I
LOL
V
OUT
= 0 V –3 µ A
current, low
On-chip pull-up resistor R L V IN = 0 V Ports 0, 1, 2, 3, 6, 8, and 9 50 100 200 k Ω
(Excluding P00 pin)
Port 5
(N-ch open-drain)
When input
instruction is
executed