Renesas R61509V - Manual (Page 101)

R61509V Target Spec
Rev. 0.11 April 25, 2008, page 101 of 181
80-System 16-bit Bus Interface
A1
HWR
RS
WR :
16
R61509V
HOST
PROCESSOR
IM[2:0] = 010
CSn
(RD :) (RD :)
D15-0
CS :
DB17-10, 8-1
Figure 17 16-bit Interface
Instruction
DB
17
DB
16 DB
15 DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB DB
5
DB
4
DB
3
DB
2
DB
1
IB
15
IB IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0 14
6
Instruction
Input
Instruction code
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
IB
15
IB IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0 14
6
Instruction code
Device code read / Instruction read
Device code
Output
Note: Device code cannot be read in 2 transfer mode.
Figure 18 16-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)