Renesas R61509V - Manual (Page 70)

R61509V Target Spec
Rev. 0.11 April 25, 2008, page 70 of 181
DC0 [2:0]: Sets step-up clock frequency for Step-up Circuit 1. The step-up clock is in synchronization
with internal clock.
Table 43 Step-up Frequency (Step-up Circuit 2)
Note 1: Make sure that fDCDC1 ≥ fDCDC2.
Note 2: Set DC0 and RTN* so that ((DCDC1 step-up frequency) ≤ (Line frequency). If not, step-up operation
may not be completed satisfactory.
The step-up frequencies synchronize with display operation. Clock count is reset at the beginning of 1H
period.
DC0[2:0]
Step-up Circuit 1
Step-up frequency (fDCDC1)
3’h0 Step-up circuit 1 halts
3’h1 Setting inhibited
3’h2 Setting inhibited
3’h3 Setting inhibited
3’h4 FOSC / 8
3’h5 FOSC / 16
3’h6 FOSC / 32
3’h7 Setting inhibited
fosc : Internal clock frequency
Division ratio : DIV*[1:0] ((DIVI or DIVE)
N : DC1 [2:0]
Step-up clock frequency (f
DCDC1
) =
Internal clock frequency f
OSC
[Hz]
[Step-up clock frequency for Step-up Circuit 1]
Number of clock per line x Division ratio x 2 (N-1)
Line frequency
2 (N-1)
=
[Hz]