Renesas R61509V - Manual (Page 13)

R61509V Target Spec
Rev. 0.11 April 25, 2008, page 13 of 181
4. Graphics RAM (GRAM)
GRAM stands for graphics RAM, which can store bit-pattern data of 233,280 (240RGB x 432 (dots) x
18(bits)) bytes at maximum, using 18 bits per pixel.
5. Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates liquid crystal drive voltages according to the grayscale
data in the γ-correction registers to enable 262k-color display. For details, see the γ-Correction Register
section.
6. Liquid Crystal Drive Power Supply Circuit
The liquid crystal drive power supply circuit generates DDVDH, VGH, VGL and VCOM levels to drive
liquid crystal.
7. Timing Generator
The timing generator generates a timing signal for the operation of internal circuits such as the internal
GRAM. The timing signal for display operations such as RAM read and the timing signal for internal
operations such as RAM access from the host processor are generated separately in order to avoid mutual
interference.
8. Oscillator (OSC)
The R61509V generates the RC oscillation clock internally. Using an external oscillation resistor is not
possible. The oscillation frequency is set to 678 kHz before shipment (for details, see Electrical
Characteristics). Use the frame frequency adjustment function to change the number of display lines and
the frame frequency. While the R61509V is shut down, RC oscillation halts so that reduce power
consumption is reduced.
9. Liquid crystal driver Circuit
The liquid crystal driver circuit of the R61509V consists of a 720-output source driver (S1 ~ S720) and a
432-output gate driver (G1~G432). The display pattern data is latched when all of 240RGB data are
inputted. The latched data control the source driver and output drive waveforms. The gate driver for
scanning gate lines outputs either VGH or VGL level. The shift direction of 720-bit source output from the
source driver can be changed by setting the SS bit and the shift direction of gate output from the gate driver
can be changed by setting the GS bit. The scan mode by the gate driver can be changed by setting the SM
bit.
10. Internal Logic Power Supply Regulator
The internal logic power supply regulator generates internal logic power supply VDD.