Renesas R61509V - Manual (Page 109)

R61509V Target Spec
Rev. 0.11 April 25, 2008, page 109 of 181
Serial Interface
The serial interface is selected by setting the IM2/1 pins to the IOVCC/GND levels, respectively. The data
is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and
serial data output line (SDO). In serial interface operation, the IM0_ID pin functions as the ID pin, and the
DB17-0 pins, not used in this mode, must be fixed at either IOVCC or GND level.
The R61509V recognizes the start of data transfer on the falling edge of CSX input and starts transferring
the start byte. It recognizes the end of data transfer on the rising edge of CSX input. The R61509V is
selected when the 6-bit chip address in the start byte transferred from the transmission unit and the 6-bit
device identification code assigned to the R61509V are compared and both 6-bit data match. Then, the
R61509V starts taking in subsequent data. The least significant bit of the device identification code is
determined by setting the ID pin. Send "01110” to the five upper bits of the device identification code.
Two different chip addresses must be assigned to the R61509V because the seventh bit of the start byte is
register select bit (RS). When RS = 0, index register write operation is executed. When RS = 1, either
instruction write operation or RAM read/write operation is executed. The eighth bit of the start byte is R/W
bit, which selects either read or write operation. The R61509V receives data when the R/W = 0, and
transfers data when the R/W = 1.
When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred
in two bytes. The R61509V writes data to the GRAM in units of 18 bits by adding the same bits as the
MSBs to the LSB of R and B dot data.
After receiving the start byte, the R61509V starts transferring or receiving data in units of bytes. The
R61509V transfers data from the MSB. The R61509V’s instruction consists of 16 bits and it is executed
inside the R61509V after it is transferred in two bytes (16 bits: DB15-0) from the MSB. The R61509V
expands RAM write data into 18 bits when writing them to the internal GRAM. The first byte received by
the R61509V following the start byte is recognized as the upper eight bits of instruction and the second
byte is recognized as the lower 8 bits of instruction.
When reading data from the GRAM, valid data is not transferred to the data bus until first five bytes of data
are read from the GRAM following the start byte. The R61509V sends valid data to the data bus when it
reads the sixth and subsequent byte data.
Table 58 Start Byte Format
Transferred Bits S 1 2 3 4 5 6 7 8
Start byte format Transfer start Device ID code
0 1 1 1 0 ID
RS R/W
Note: The ID bit is determined by setting the IM0_ID pin.
Table 59 Functions of RS, R/W Bits
RS R/W Function
0 0 Set index register
0 1 Setting inhibited
1 0 Write instruction or RAM data
1 1 Read instruction or RAM data