Texas Instruments Dual/Single Socket CardBus and UntraMedia Controller PCI7621 - Manual (Page 197)

8−17
Table 8−13. Isochronous Receive Channel Mask High Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
6 isoChannel38 RSC When bit 6 is set to 1, the controller is enabled to receive from isochronous channel number 38.
5 isoChannel37 RSC When bit 5 is set to 1, the controller is enabled to receive from isochronous channel number 37.
4 isoChannel36 RSC When bit 4 is set to 1, the controller is enabled to receive from isochronous channel number 36.
3 isoChannel35 RSC When bit 3 is set to 1, the controller is enabled to receive from isochronous channel number 35.
2 isoChannel34 RSC When bit 2 is set to 1, the controller is enabled to receive from isochronous channel number 34.
1 isoChannel33 RSC When bit 1 is set to 1, the controller is enabled to receive from isochronous channel number 33.
0 isoChannel32 RSC When bit 0 is set to 1, the controller is enabled to receive from isochronous channel number 32.
8.20 Isochronous Receive Channel Mask Low Register
The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous
data channels. See Table 8−14 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Isochronous receive channel mask low
Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Isochronous receive channel mask low
Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC
Default X X X X X X X X X X X X X X X X
Register: Isochronous receive channel mask low
Offset: 78h set register
7Ch clear register
Type: Read/Set/Clear
Default: XXXX XXXXh
Table 8−14. Isochronous Receive Channel Mask Low Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 isoChannel31 RSC When bit 31 is set to 1, the controller is enabled to receive from isochronous channel number 31.
30 isoChannel30 RSC When bit 30 is set to 1, the controller is enabled to receive from isochronous channel number 30.
29−2 isoChanneln RSC Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, … , 2) follow the same pattern as bits 31 and 30.
1 isoChannel1 RSC When bit 1 is set to 1, the controller is enabled to receive from isochronous channel number 1.
0 isoChannel0 RSC When bit 0 is set to 1, the controller is enabled to receive from isochronous channel number 0.