Texas Instruments Dual/Single Socket CardBus and UntraMedia Controller PCI7621 - Manual (Page 280)

13−8
13.11 Subsystem Identification Register
This register is read-update and can be modified through the subsystem ID alias register. This register has no effect
to the functionality. Default value is 8035h. This default value complies with the WLP (Windows Logo Program)
requirements without BIOS or EEPROM configuration. All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1
Register: Subsystem identification
Offset: 2Eh
Type: Read/Update
Default: 8035h
13.12 Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header where the
power-management register block resides. Since the PCI power management registers begin at 44h, this read-only
register is hardwired to 44h.
Bit 7 6 5 4 3 2 1 0
Name Capabilities pointer
Type R R R R R R R R
Default 0 1 0 0 0 1 0 0
Register: Capabilities pointer
Offset: 34h
Type: Read-only
Default: 44h
13.13 Interrupt Line Register
The interrupt line register is programmed by the system and indicates to the software which interrupt line the Smart
Card interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet
been assigned to the function.
Bit 7 6 5 4 3 2 1 0
Name Interrupt line
Type RW RW RW RW RW RW RW RW
Default 1 1 1 1 1 1 1 1
Register: Interrupt line
Offset: 3Ch
Type: Read/Write
Default: FFh