Texas Instruments Dual/Single Socket CardBus and UntraMedia Controller PCI7621 - Manual (Page 85)

3−29
The global reset-only (function 3) register bits:
•
Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15–0
• Subsystem ID register (PCI offset 2Eh, see Section 11.10): bits 15–0
• Power management control and status register (PCI offset 48h, see Section 11.18): bits 15, 8, 1, 0
•
General control register (PCI offset 4Ch, see Section 11.21): bits 6−4, 2–0
• Diagnostic register (PCI offset 54h, see Section 11.23): bits 31–0
The global reset-only (function 4) register bits:
• Subsystem vendor ID register (PCI offset 2Ch, see Section 12.9): bits 15–0
•
Subsystem ID register (PCI offset 2Eh, see Section 12.10): bits 15–0
•
Power management control and status register (PCI offset 84h, see Section 12.19): bits 15, 8, 1, 0
• General control register (PCI offset 88h, see Section 12.22): bits 6−4, 0
•
Diagnostic register (PCI offset 90h, see Section 12.24): bits 31–0
The global reset-only (function 5) register bits:
•
Subsystem vendor ID register (PCI offset 2Ch, see Section 13.10): bits 15–0
•
Subsystem ID register (PCI offset 2Eh, see Section 13.11): bits 15–0
• Power management control and status register (PCI offset 48h, see Section 13.19): bits 15, 8, 1, 0
•
General control register (PCI offset 4Ch, see Section 13.22): bits 6−4, 0