Rainbow Electronics T89C5121 - Manual (Page 10)

10
A/T8xC5121
4164G–SCR–07/06
Port Structure
Description The different ports structures are described as follows.
Quasi Bi-directional Output
Configuration The default port output configuration for standard I/O ports is the quasi bi-directional out-
put that is common on the 80C51 and most of its derivatives. This output type can be
used as both an input and output without the need to reconfigure the port. This is possi-
ble because when the port outputs a logic high, it is weakly driven, allowing an external
device to pull the pin low. When the port outputs a logic low state, it is driven strongly
and able to sink a fairly large current. These features are somewhat similar to an open
drain output except that there are three pull-up transistors in the quasi bi-directional out-
put that serve different purposes. One of these pull-ups, called the weak pull-up, is
turned on whenever the port latch for the pin contains a logic 1. The weak pull-up
sources a very small current that will pull the pin high if it is left floating. A second pull-
up, called the medium pull-up, is turned on when the port latch for the pin contains a
logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary
source current for a quasi bi-directional pin that is outputting a 1. If a pin that has a logic
1 on it is pulled low by an external device, the medium pull-up turns off, and only the
weak pull-up remains on. In order to pull the pin low under these conditions, the external
device has to sink enough current to overpower the medium pull-up and take the voltage
on the port pin below its input threshold.
Figure 5. Quasi Bi-directional Output Configuration
Push-pull Output
Configuration The Push-pull output configuration has the same pull-down structure as the quasi bi-
directional output modes, but provides a continuous strong pull-up when the port latch
contains a logic 1. The Push-pull mode may be used when more source current is
needed from a port output. The Push-pull port configuration is shown in Figure 5.
2 CPU
Input
Pin
Strong Weak Medium
N
P P
P
CLOCK DELAY
Port latch
Data
Data
PMOS
NMOS