Rainbow Electronics T89C5121 - Manual (Page 25)

25
A/T8xC5121
4164G–SCR–07/06
Table 9. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = X0X0 X000b
7 6 5 4 3 2 1 0
- WDX2 - SIX2 - T1X2 T0X2 X2
Bit
Number
Bit
Mnemonic Description
7 - Reserved
6 WDX2
Watchdog clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5 - Reserved
4 SIX2
Enhanced UART clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3 - Reserved
2 T1X2
Timer 1 clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1 T0X2
Timer 0 clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
0 X2
CPU clock
Clear to select 12 clock periods per machine cycle (Standard mode) for CPU
and all the peripherals.
Set to select 6 clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.