Dual data pointer – Rainbow Electronics T89C5121 User Manual
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A/T8xC5121
4164G–SCR–07/06
Dual Data Pointer
T8xC5121 contains a Dual Data Pointer accelerating data memory block moves. The
Standard 80C52 Data Pointer is a 16-bit value that is used to address off-chip data RAM
or peripherals. In T8xC5121, the standard 16-bit data pointer is called DPTR and
located at SFR location 82H and 83H. The second Data Pointer named DPTR1 is
located at the same address than the previous one. The DPTR select bit (DPS / bit0)
chooses the active pointer and it is located into the AUXR1 register. It should be ser-
viced in those sections of code that will periodically be executed within the time required
to prevent a WDT reset.
The user switches between data pointers by toggling the LSB of the AUXR1. The incre-
ment (INC) is a solution for this. All DPTR-related instructions use the currently selected
DPTR for any activity. Therefore only one instruction is required to switch from a source
to a destination address. Using the Dual Data Pointer saves code and resources when
moves of blocks need to be accomplished.
The second Data Pointer can be used to address the on-chip XRAM.
Table 41. DPL Register
DPL - Low Byte of DPTR1 (82h)
Reset value = 0000 0000b
Table 42. DPH Register
DPH - High Byte of DPTR1 (83h)
Reset value = 0000 0000b
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-