Clock management, Functional block diagram – Rainbow Electronics T89C5121 User Manual
Page 22
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22
A/T8xC5121
4164G–SCR–07/06
Clock Management
In order to optimize the power consumption and the execution time needed for a specific
task, an internal prescaler feature and a X2 feature have been implemented between
the oscillator and the CPU.
Functional Block
Diagram
Figure 11. Clock Generation Diagram
If CKRL<>7 then:
If CKRL = 7 then:
CKRL
Prescalor Factor
7
1
6
2
5
4
4
6
3
8
2
10
1
12
0
14
1
2
F
OSC
1
2(7-CKRL)
CKRL = 7
X2
F
CLK_Periph
F
CLK_CPU
CKCON0
CKRL
F
OSC
2
x2
0
1
0
1
Osc.
XTAL1
XTAL2
F
CLK
CPU
–
F
O SC
2 x2
( )
-----------------
x
1
2 7
C KR L
–
(
)
-----------------------------------
=
F
C LK
CPU
–
Fosc
2x2
--------------
=
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