Rainbow Electronics T89C5121 - Manual (Page 16)

16
A/T8xC5121
4164G–SCR–07/06
Power Monitoring
and Clock
Management
For applications where power consumption is a critical factor, three power modes are
provided:
• Idle mode
• Power-down mode
• Clock Management (X2 feature and Clock Prescaler)
• 3V Regulator Modes (pulsed or not pulsed)
Idle Mode An instruction that sets PCON.0 causes the last instruction to be executed before going
into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but
not to the interrupt, Timer 0, and Serial Port functions. The CPU status is preserved in
its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator
and all other registers maintain their data during Idle. The port pins hold the logical
states they had at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-
viced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bit GF0 can be used to give an indication if an interrupt occurred during normal
operation or during an Idle. For example, an instruction that activates Idle can also set
one or both flag bits. When Idle is terminated by an interrupt, the interrupt service rou-
tine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
Entering Power-down Mode To save maximum power, a Power-down mode can be invoked by software (refer to
Table 3, PCON register).
In Power-down mode, the oscillator is stopped and the instruction that invoked Power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated.
V
CC
can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from Power-
down. To properly terminate Power-down, the reset or external interrupt should not be
executed before
V
CC
is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from Power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 10. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and Power-Down exit will be completed when the
first input will be released. In this case the higher priority interrupt service routine is
executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put it into Power-down mode.
Exit from Power-down Mode Exiting from Power-down by external interrupt does not affect the SFRs and the internal
RAM content.