Rainbow Electronics T89C5121 - Manual (Page 77)

77
A/T8xC5121
4164G–SCR–07/06
Timer 1 Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The fol-
lowing comments help to understand the differences:
• Timer 1 functions as either a Timer 0 or an event Counter in the three operating
modes. Figure 28 through Figure 30 show the logical configuration for modes 0, 1,
and 2. Mode 3 of Timer 1 is a hold-count mode.
• Timer 1 is controlled by the four high-order bits of the TMOD register (see Figure 56)
and bits 2, 3, 6 and 7 of the TCON register (see Figure 55). The TMOD register
selects the method of Timer 0 gating (GATE1), Timer 0 or Counter operation
(C/T1#) and the operating mode (M11 and M01). The TCON register provides Timer
1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and
the interrupt type control bit (IT1).
• Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best
suited for this purpose.
• For normal Timer 0 operation (GATE1 = 0), setting TR1 allows TL1 to be
incremented by the selected input. Setting GATE1 and TR1 allows external pin
INT1
to control Timer 0 operation.
• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag and
generates an interrupt request.
• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use Timer 1 only for applications that do not require an
interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in
and out of mode 3 to turn it off and on.
• It is important to stop the Timer 0/Counter before changing modes.
Mode 0 (13-bit Timer 0) Mode 0 configures Timer 1 as a 13-bit Timer 0, which is set up as an 8-bit Timer 0 (TH1
register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 regis-
ter (see Figure 28). The upper 3 bits of TL1 register are ignored. Prescaler overflow
increments the TH1 register.
Mode 1 (16-bit Timer 0) Mode 1 configures Timer 1 as a 16-bit Timer 0 with TH1 and TL1 registers connected in
cascade (see Figure 29). The selected input increments the TL1 register.
Mode 2 (8-bit Timer 0 with
Auto-Reload) Mode 2 configures Timer 1 as an 8-bit Timer 0 (TL1 register) with automatic reload from
the TH1 register on overflow (see Figure 30). TL1 overflow sets the TF1 flag in the
TCON register and reloads TL1 with the contents of TH1, which is preset by the soft-
ware. The reload leaves TH1 unchanged.
Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt
Timer 1 when the TR1 run control bit is not available i.e., when Timer 0 is in mode 3.