Agilent Technologies VXI E1439 - Manual (Page 224)

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Module Description
Block diagram and description
In a system using more than one E1439, the ADCs can be synchronized by programming them to
use a common SYNC reference, available via the front panel or backplane. One of the modules
can be the master that drives this SYNC line. This master SYNC can be extended to other
mainframes by connecting an "Intermodule Clock" SMB connector to an "Intermodule Clock"
SMB connector on an E1439 in the second mainframe.
Anti-alias Filter
Since the ADC sample rate is 95 MHz, a complete representation of the input signal can be
achieved only for bandwidths up to 47.5 MHz (47.5 - 95 MHz for the 70MHz IF and 0 - 47.5
MHz for baseband). Frequency components outside the 47.5 MHz bandwidth can cause
ambiguous results (aliasing).
The 70 MHz IF filter attenuates frequency components both below and above 52 - 88 MHz to
reduce aliasing. This filter rejects signals from 0 - 43 MHz and 102 - 200 MHz to 78 dB. Thus
the 52 - 88 MHz frequency range of the sampled signal is 78 dB alias free. The filter's transition
bands from 43-52 MHz and 88 - 102 MHz affects flatness and allows some aliasing in the
sampled signal frequency ranges 47.5-52 MHz and 88 - 95 MHz.
The baseband anti-alias filter attenuates high frequency components to reduce aliasing. This filter
is flat to 36 MHz and rejects signals above 59 MHz to 65 dB. Thus the 0-36 MHz frequency range
of the sampled signal is 65 dB alias free. The filter's transition band from 36 to 59 MHz affects
flatness and allows some aliasing in the sampled signal frequency range 36 to 47.5 MHz.
In cases where alias filtering is not necessary, the E1439 can be programmed to bypass the anti-
alias filter. To avoid incorrect results, the alias filter bypass mode should be used with caution; it
is not recommended for normal operation.
Ext Clock/Ref
BNC.
Intermodule
Clock
SMB
Local
VXI
SMB
BNC
VXI
Phase
detector
95 MHz
VCXO
÷ 38
2.5 MHz
VXI Bus
Ref Clk
Sample
Clk. to ADC
95 Mhz
ч
ч
4
or
1