Agilent Technologies VXI E1439 - Manual (Page 219)

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Module Description
VXI backplane connections
VXI backplane connections
Power Supplies and Ground
The E1439 conforms to the VME and VXI specifications for pin assignment. The current drawn
from each supply is listed in the Technical Specifications.
Data Transfer Bus
The E1439 conforms to the VME and VXI specifications for pin assignment and protocol. Only
A16/D16/D32 data transfers are supported, thus the upper addresses are ignored.
DTB Arbitration Bus
The E1439 is not capable of requesting bus control, thus it does not use the Arbitration bus. To
conform to the VME and VXI specifications, it passes the bus lines through.
Priority Interrupt Bus
The E1439 generates interrupts by applying a programmable mask to its status bits. The priority
of the interrupt is determined by the interrupt priority setting in the control register.
Utility Bus
The VME specification provides a set of lines collectively called the utility bus. Of these lines, the
E1439 only uses the SYSRESET* line.
Pulling the SYSRESET* line low (a hardware reset) has the same effect as setting the reset bit in
the Control Register (a software reset), with two exceptions. The exceptions are:
• The Control Register is also reset.
• All logic arrays are reloaded.
Reloading the logic arrays enables the hardware reset to recover from power dropouts, which may
invalidate the logic setup.
Local Bus
The VXI specification includes a 12-wire local bus between adjacent module slots. Using the
local bus, Agilent Technologies has defined a standard byte-wide ECL protocol that transfers data
from left to right at up to 100 Mbyte/second. The E1439D can be programmed to output its data
using this high speed port instead of the VME data output register. The Data Port Control register
determines which output port is used.