Agilent Technologies VXI E1439 - Manual (Page 42)

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Using the Agilent E1439
Managing multiple modules
Managing multiple modules
Sharing Reference and Sync signals in multi-module systems
The Agilent E1439 supports synchronous operation among multiple E1439s by using a shared
ADC clock and Sync signal to drive all the modules in a system. The shared Sync signal is used to
synchronize critical operations including arming, triggering the beginning of data collection,
setting a common phase of the local oscillators for zoom operation, and forcing concurrent output
sample times when decimation is used. The Sync line transitions are constrained to not occur
during the critical (setup and hold) regions of the external reference. The reference operates at
1/38 of the internal ADC clock, typically 95 MHz for a E1439 module. The reference can be
either generated within the master module or an external reference can be fed into the master
module through a front panel BNC.
Note
For optimal phase noise performance in multi-module systems it is recommended that the first
channel be an Agilent E1439C or D
1
. The Agilent E1439C does not support local bus or fiber
optic transfers.
Note
Multi-module systems may include multiple Agilent E1438s or Agilent E1439s but not a mixture
of the two types of modules.
Clock distribution
When shared, the reference clock and sync lines are distributed among modules either on the VXI
backplane using the ECL Trigger lines, or on the front panel using the SMB Clock/Ref extender
connectors. When VXI backplane distribution is used with more than one VXI mainframe, the
front panel Intermodule Clock and Sync connectors can be used to distribute clock and Sync lines
from one mainframe to another.
Since the Sync transition timing relative to the reference input is critical, the module driving the
Sync line should ideally be the same one identified as the master. However, when using backplane
distribution, any E1439 in the same mainframe as the master can drive the Sync line.
When using the multi-sync mode of operation, the selection of front panel or backplane
distribution of reference and Sync signals involves the following considerations:
• Backplane distribution requires the use of the ECL Trigger lines on the backplane, which are
then unavailable to other modules.
• The overall time skew between the arrival of ADC clock edges is smaller when using
backplane distribution, particularly if the master (or buffer) module is physically located in
the center of the group of E1439 modules.
• Backplane distribution is more susceptible to pickup of jitter on the ADC clock from other
digital activity on the VXI backplane. The extent of this pickup depends on the mainframe and
on the other modules in the mainframe. One important step in reducing this pickup is to
disable, whenever possible, the 10 MHz VXI clock generated by the slot-0 controller.
1
As opposed to the older A or B models.