Rockwell Automation 1747-DCM,D17476.8 Direct Communication Module - Manual (Page 50)

Chapter 6
Programming
6–8
To ensure that the DCM output Data Invalid bit is cleared (signifying to the
RIO scanner’s supervisory processor that data is valid), the SLC ladder logic
rung shown below must be included as the last rung in your SLC ladder logic
program.
O:3.0
10
SLC Rung
addresses bit 10 (decimal);
RIO Scanner ’s supervisory
processor receives bit 12 (octal).
(U)
The RIO scanner’s supervisory processor ladder logic program should use
the DCM output Data Invalid bit to condition any supervisory processor
outputs whose state is dependent upon valid data from the DCM/distributed
SLC. An example of a PLC-5 processor rung that requires this conditioning
is shown below.
] [
I:021
00
]/[
I:020
12
( )
O:000
00
PLC-5 Rung
SLC addresses bit 10 (decimal);
PLC receives bit 12 (octal).
This rung uses data from the DCM (word 1, bit 0 PLC address I:021/00) to
energize a PLC-5 output: bit 0, of rack 0, module group 0. It is conditioned
with the Data Invalid bit. By using the DCM output Data Invalid bit in this
example, the PLC-5 will not energize the output shown above unless the data
received from the SLC/DCM is valid.
Using the User Status Flag Bit
This status bit (13) is available for your particular application. It is cleared
on powerup and thereafter is never operated on by the DCM. After powerup
this bit is only set (1) or cleared (0) by your SLC ladder logic program.
A typical application using this bit would be to inform the RIO scanner’s
supervisory processor that the SLC is disabling the slot where the DCM is
located. If the DCM slot is disabled while the SLC is in the Run Mode, data
sent to the RIO scanner will be last state data (invalid). Without using the
User Status Flag bit, no indication that data is not being updated would be
sent to the RIO scanner (that is, neither the Program/Test/Fault Mode bit nor
the Invalid Data bit would be set). If your SLC ladder logic program sets the
User Status Flag bit prior to disabling the DCM slot, the supervisory
processor can use this bit in its ladder logic where appropriate.
!
ATTENTION: Make certain that you have thoroughly examined
the effects of disabling the DCM slot before doing so in your
application.
An example of how rungs might be programmed in the two processors to
indicate disabling of the DCM slot is shown on the next page.