A.4.1.2 base + 01h telclock1: pll control & status – Kontron AT8050 User Manual
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A.4.1.2
Base + 01h TelClock1: PLL Control & Status
Offset
Action
D7
D6
D6
D4
D3
D2
D1
D0
01h
Read
LOCK
FAIL1
FAIL0
0
TIE_CLR#
MODE
RESET
OOR
Write
NU
NU
NU
NU
TIE_CLR#
MODE
RESET
OOR
Reset
NA
NA
NA
NA
1
1
0
0
Name
Description
LOCK
PLL lock status.
1: PLL locked
0: PLL not locked (PLL in holdover or free running)
FAIL1
REF1 (CLK1B or CLK2B according to BP_REF) failed with current OOR setting. Same as FAIL0 but for
REF1.
FAIL0
REF0 (CLK1A or CLK2A according to BP_REF) failed with current OOR setting.
1: failed clock.
0: passed clock.
TIE_CLR#
Timing-Interval-Error adjustement.
1: normal mode.
0: adjust phase to match reference.
MODE
PLL operating mode.
1: freerun mode(may be used for tests).
0: normal mode.
RESET
Hardware reset of the PLL. This bit is forced to ‘1’ when the payload power (i.e. PLL power) is turned
off.
1: reset
0: normal operation
OOR
OUT-OF-Range selection. Determine what is considered a precision fault by the PLL.
1: 64 - 83ppm.
0: 40 - 52ppm.
Note:
This register needs to be reprogrammed every time the blade is resetted. Those are direct pin
control and status. See the ZL30108 datasheet for a detailed explanation of the functionality.