Kontron AT8050 User Manual
Page 146
A-10
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A.4.1.6
Base + 05h TelClock5: Clock Events & Alarm (IPMC only)
Offset
Action
D7
D6
D6
D4
D3
D2
D1
D0
05h
Read
LOCKE
FAIL1E
FAIL0E
SELREFE
0
0
0
0
Write
Clear
Clear
Clear
Clear
NU
NU
NU
NU
Reset
X*
X*
X*
X*
NA
NA
NA
NA
Name
Description
LACKE
Same as FAIL0 but for the lock status of the PLL. This bit captures the “unlock” state. This would
typically be used to generate an alarm.
FAIL1E
Same as FAIL0 but for reference 1.
FAIL0E
This bit captures the assertion of a failure on reference 0 on the PLL. This is basically a short failure
detection that the IPMC would otherwise miss. Use Telco+1 to read the current state. To Clear this bit,
write a 1 in it. The bit will be cleared even if there is still a fauld on this clock.
SELREFE
Same as FAIL0 but for the selected reference. This bit goes to one everytime the selected reference
changes. This is just to inform the software that a reference change occured.
Note:
* unpredictable: need to be cleared by IPMC on power up.
Events and alarms are implemented in the FPGA. The FPGA build them using the raw signals from the
first three registers.
Note that this register is only available on the IPMC side of the interface.