Mapping pfl and flash address – Altera Parallel Flash Loader IP User Manual
Page 13
You can use the PFL IP core to either program the flash memory devices, configure your FPGA, or both;
however, to perform both functions, create separate PFL functions if any of the following conditions apply
to your design:
• You want to use fewer LEs.
• You modify the flash data infrequently.
• You have JTAG or In-System Programming (ISP) access to the Altera CPLD.
• You want to program the flash memory device with non-Altera data. For example, the flash memory
device contains initialization storage for an ASSP. You can use the PFL IP core to program the flash
memory device with the initialization data and also create your own design source code to implement
the read and initialization control with the CPLD logic.
Creating Separate PFL Functions
To create separate PFL functions, follow these steps:
1. To create a PFL instantiation, select Flash Programming Only mode.
2. Assign the pins appropriately.
3. Compile and generate a
.pof
for the flash memory device. Ensure that you tri-state all unused I/O pins.
4. To create another PFL instantiation, select Configuration Control Only mode.
5. Instantiate this configuration controller into your production design.
6. Whenever you must program the flash memory device, program the CPLD with the flash memory
device
.pof
and update the flash memory device contents.
7. Reprogram the CPLD with the production design
.pof
that includes the configuration controller.
Note: All unused pins are set to ground by default. When programming the configuration flash memory
device through the CPLD JTAG pins, you must tri-state the FPGA configuration pins common to
the CPLD and the configuration flash memory device. You can use the
pfl_flash_access_request
and
pfl_flash_access_granted
signals of the PFL block to tri-state
the correct FPGA configuration pins.
Related Information
•
on page 13
•
Implementing Page in the Flash .pof
•
Using Enhanced Bitstream Compression and Decompression
•
on page 20
Mapping PFL and Flash Address
The address connections between the PFL IP core and the flash memory device vary depending on the
flash memory device vendor and data bus width.
UG-01082
2015.01.23
Mapping PFL and Flash Address
13
Parallel Flash Loader IP Core User Guide
Altera Corporation