Altera Parallel Flash Loader IP User Manual

Page 46

Advertising
background image

Pin

Description

Weak Pull-

Up

Function

flash_nce[]

Output

Connects to the

nCE

pin of the flash memory

device. A low signal enables the flash

memory device. Use this pin for multiple

flash memory device support. The

flash_

nce

pin is connected to each

nCE

pin of all

the connected flash memory devices. The

width of this port depends on the number of

flash memory devices in the chain.

flash_nwe

Output

Connects to the

nWE

pin of the flash memory

device. A low signal enables write operation

to the flash memory device.

flash_noe

Output

Connects to the

nOE

pin of the flash memory

device. A low signal enables the outputs of

the flash memory device during a read

operation.

flash_clk

Output

Used for burst mode. Connects to the

CLK

input pin of the flash memory device. The

active edges of

CLK

increment the flash

memory device internal address counter.

The

flash_clk

frequency is half of the

pfl_

clk

frequency in burst mode for single CFI

flash. In dual P30 or P33 CFI flash solution,

the

flash_clk

frequency runs at a quarter of

the

pfl_clk

frequency. Use this pin for burst

mode only. Do not connect these pins from

the flash memory device to the CPLD device

if you are not using burst mode.

flash_nadv

Output

Used for burst mode. Connects to the

address valid input pin of the flash memory

device. Use this signal for latching the start

address. Use this pin for burst mode only.

Do not connect these pins from the flash

memory device to the CPLD device if you

are not using burst mode.

flash_nreset

Output

Connects to the reset pin of the flash

memory device. A low signal resets the flash

memory device.

fpga_data[]

Output

Data output from the flash to the FPGA

device during configuration. For PS mode,

this is a 1-bit bus

fpga_data[0]

data line.

For FPP mode, this is an 8-bit

fpga_

data[7..0]

data bus. This pins are not

available for the flash programming option

in the PFL IP core.

46

Signals

UG-01082

2015.01.23

Altera Corporation

Parallel Flash Loader IP Core User Guide

Send Feedback

Advertising