Programming multiple flash memory devices, Pfl ip core in embedded systems – Altera Parallel Flash Loader IP User Manual
Page 35
Related Information
Supported Flash Memory Devices
on page 2
Programming Multiple Flash Memory Devices
The PFL IP core supports multiple-flash programming of as many as 16 flash memory devices. This
feature allows the PFL IP core to connect to multiple flash memory devices to perform flash programming
sequentially. PFL multiple-flash programming supports both speed and area mode flash programming.
For FPGA configuration, use the content in the flash memory device that connects to the
nCE[0]
pin as
configuration data.
To use the multiple flash programming feature, follow these steps:
1. Select the number of flash memory devices connected to the CPLD in the PFL IP core parameter
editor.
2. Connect the
nCE
pins of the PFL to the
nCE
pins of the flash memory device in the block diagram.
Compile the design.
3. Click Auto Detect in the Quartus II programmer. The CPLD appears as the main item, followed by a
list of CFI flash memory devices detected as secondary items in the device tree.
4. Attach the flash memory device
.pof
to each flash memory device.
5. Check the boxes in the Quartus II Programmer for the necessary operation and click Start.
Creating Jam Files for Altera CPLDs and Flash Memory Device Programming
To use .jam files to program the CPLD and flash memory device, follow these steps:
1. Open the Quartus II Programmer window and click Add File to add the
.pof
for the CPLD.
2. Right-click the CPLD
.pof
and click Attach Flash Device.
3. In the Flash Device menu, select the density of the flash memory device to be programmed.
4. Right-click the necessary flash memory device density and click Change File.
5. Select the
.pof
generated for the flash memory device. The
.pof
for the flash memory device is attached
to the
.pof
of the CPLD.
6. On the File menu, point to Create/Update and click Create JAM, JBC, SVF, or ISF File.
7. Enter a name and select the file format (
.jam
).
8. Click OK.
Note: Use the
.jam
files with the Quartus II Programmer or
quartus_jli
executable file.
Related Information
Provides more information about the quartus_jli executable.
PFL IP Core In Embedded Systems
The PFL IP core allows processors, such as the Nios
®
II processor, to access the flash memory device
while programming flash and configuring an FPGA.
The following figure shows how you can use the PFL IP core to program the flash memory device and to
configure the FPGA with a Nios II processor. The configured Nios II processor uses the non-configura‐
tion data stored in the same flash memory device.
UG-01082
2015.01.23
Programming Multiple Flash Memory Devices
35
Parallel Flash Loader IP Core User Guide
Altera Corporation