Constraining pfl timing, Constraining clock signal – Altera Parallel Flash Loader IP User Manual
Page 26
• Typical bitstream compression feature
1. Select
.sof
under SOF Data.
2. Click Properties, and then turn on the Compression option.
3. Click OK.
• Enhanced bitstream compression feature
1. In the Options dialog box, turn on the Enable enhanced bitstream-compression when
available option.
2. Click OK.
• Double compression technique
• Perform all the steps for the typical bitstream compression and enhanced bitstream compression
features listed above.
Note: For more information about the compression feature in the PFL IP core, refer to “Using
Enhanced Bitstream Compression and Decompression”.
12.To generate programming files with encrypted data, select
.sof
under SOF Data and click Properties.
Turn on the Generate encrypted bitstream check box.
13.Click OK to create the
.pof
.
Related Information
Using Enhanced Bitstream Compression and Decompression
Constraining PFL Timing
The PFL IP core supports the Quartus II TimeQuest Timing Analyzer for accurate timing analysis on the
Altera IP cores. To perform timing analysis, you must define the clock characteristics, external path
delays, and timing exceptions for the PFL input and output ports. This section provides guidelines for
defining this information for PFL input and output ports for use by the TimeQuest analyzer.
Note: The TimeQuest analyzer is a timing analysis tool that validates the timing performance of the logic
in the design using industry-standard constraint, analysis, and reporting methodology. For more
information about the TimeQuest analyzer, refer to the Quartus II TimeQuest Timing Analyzer
chapter in volume 3 of the Quartus II Handbook.
Note: After you specify the timing constraint settings for the clock signal and for the asynchronous and
synchronous input and output ports in the TimeQuest analyzer, on the Constraints menu, click
Write SDC File to write all the constraints to a specific System Design Constraints File (
.sdc
). After
the
.sdc
is written, run full compilation for the PFL design.
Related Information
Provides more information about the TimeQuest analyzer.
Constraining Clock Signal
At any given time, one of the following two clock sources clocks the blocks and modules of the PFL IP
core:
• Clock signals from the
pfl_clk
ports of the PFL during FPGA configuration
•
TCK
pins of the JTAG programming interface during flash programming
26
Constraining PFL Timing
UG-01082
2015.01.23
Altera Corporation
Parallel Flash Loader IP Core User Guide