Altera Parallel Flash Loader IP User Manual
Page 18
CFI Device (Megabit)
Address Range
16
0x0000000
–
0x01FFFFF
32
0x0000000
–
0x03FFFFF
64
0x0000000
–
0x07FFFFF
128
0x0000000
–
0x0FFFFFF
256
0x0000000
–
0x1FFFFFF
512
0x0000000
–
0x3FFFFFF
1024
0x0000000
–
0x7FFFFFF
Using Enhanced Bitstream Compression and Decompression
The enhanced bitstream compression and decompression feature in the PFL IP core reduces the size of
the configuration file in the flash memory device. On average, you can reduce the file size by as much as
50% depending on the designs. When you turn on the enhanced bitstream compression feature, the PFL
IP core disables data encryption.
Table 6: Comparison Between Typical, Enhanced, and Double Compression
FPGA Configuration
Typical Bitstream
Compression Feature
Enhanced Bitstream
Compression Feature
Double Compression
Technique
FPGA on-chip bitstream
decompression enabled
Yes
No
Yes
PFL enhanced bitstream
decompression enabled
No
Yes
Yes
Typical configuration file size
reduction
35%–55%
45%–75%
40%–60%
PS configuration time
Moderate
(5)
Slow
Moderate
(5)
FPP configuration time
Fast
(6)
Very fast
(7)
Not supported
Note: When using the PFL with compression, set the device MSEL pins set for compression or
decompression. When generating or converting a programming file, you can enable compression.
In the first few bytes during the generation of the programming file (with compression enabled), a
bit set notifies the PFL that the incoming files is a compressed file. The ×4 DCLK-to-data are
handled automatically in the PFL.
Note: For more information about the typical data compression feature, refer to the Configuration Data
Decompression section in the configuration chapter of the relevant device handbook.
(5)
The FPGA receives compressed bitstream which decreases the duration to transmit the bitstream to the
FPGA.
(6)
For FPP with on-chip bitstream decompression enabled, the DCLK frequency is ×2, ×4, or ×8 the data rate,
depending on the device. You can check the relationship of the DCLK and data rate in the FPP
Configuration section in the configuration chapter of the respective device handbook.
(7)
For FPP with enhanced bitstream decompression enabled, the DCLK frequency is ×1 the data rate.
18
Using Enhanced Bitstream Compression and Decompression
UG-01082
2015.01.23
Altera Corporation
Parallel Flash Loader IP Core User Guide