Altera Parallel Flash Loader IP - Manual (Page 27)

The clock signal on the
TCK
pins is internally constrained to the maximum frequency supported by the
selected JTAG programming hardware. It is not necessary to constrain the clock signal.
You can constrain
pfl_clk
to the maximum frequency that the PFL IP core supports. You can use the
create_clock
command or the Create Clock dialog box to specify the period and duty cycle of the clock
constraint.
To constrain the
pfl_clk
signal in the TimeQuest analyzer, follow these steps:
1. Run full compilation for the PFL design. Ensure that the timing analysis tool is set to
TimeQuest
Timing Analyzer
.
2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch
the TimeQuest analyzer window.
3. In the Tasks list, under Diagnostic, click Report Unconstrained Paths to view the list of
unconstrained parts and ports of the PFL design.
4. In the Report list, under Unconstrained Paths, click Clock Summary to view the clock that requires
constraints. The default setting for all unconstrained clocks is 1 GHz. To constrain the clock signal,
right-click the clock name and select Edit Clock Constraint.
5. In the Create Clock dialog box, set the period and the duty cycle of the clock constraint.
6. Click Run.
Constraining Synchronous Input and Output Ports
The setup and hold time of synchronous input and output ports is critical to the system designer. To
avoid setup and hold time violations, you can specify the signal delay from the FPGA or the flash memory
device to the synchronous input and output ports of the PFL IP core. The Quartus II Fitter places and
routes the input and output registers of the PFL IP core to meet the specified timing constraints.
Note: For more information about the synchronous input and output ports of the PFL IP core, refer to
PFL Timing Constraints table.
The signal delay from FPGA or flash memory device to the PFL synchronous input port is specified by
set_input_delay. The delay calculation is:
Input delay value = Board delay from FPGA or flash output port to the PFL input port + T
CO
of the FPGA
or flash memory device
The signal delay from PFL synchronous output port to FPGA or flash memory device is specified by
set_output_delay. The delay calculation is:
Output delay value = Board delay from the PFL output port to the FPGA or flash input port + T
SU
of
FPGA or flash device.
Note: T
CO
is the clock-to-output time from the timing specification in the FPGA, CPLD or flash
datasheet.
UG-01082
2015.01.23
Constraining Synchronous Input and Output Ports 27
Parallel Flash Loader IP Core User Guide Altera Corporation
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