Altera Parallel Flash Loader IP - Manual (Page 24)

Related Information
AN478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software
Provides more information about using the FPGA-based PFL IP core to program a flash memory device.
Customizing and Generating IP Cores
You can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog displays
IP cores available for the current target device. The parameter editor guides you to set parameter values
for optional ports, features, and output files.
To customize and generate a custom IP core variation, follow these steps:
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files
in your project. If prompted, also specify the target Altera device family and output file HDL
preference. Click OK.
3. Specify the desired parameters, output, and options for your IP core variation:
• Optionally select preset parameter values. Presets specify all initial parameter values for specific
applications (where provided).
• Specify parameters defining the IP core functionality, port configuration, and device-specific
features.
• Specify options for generation of a timing netlist, simulation model, testbench, or example design
(where applicable).
• Specify options for processing the IP core files in other EDA tools.
4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation
specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files
for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example
design for hardware testing.
5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate >
Generate Testbench System is not available for some IP cores.
6. To generate a top-level HDL design example for hardware verification, click Generate > HDL
Example. Generate > HDL Example is not available for some IP cores.
When you generate the IP variation with a Quartus II project open, the parameter editor automatically
adds the IP variation to the project. Alternatively, click Project > Add/Remove Files in Project to
manually add a top-level .qip or .qsys IP variation file to a Quartus II project. To fully integrate the IP
into the design, make appropriate pin assignments to connect ports. You can define a virtual pin to
avoid making specific pin assignments to top-level signals.
Note: By default, all unused pins are tied to ground. Altera recommends setting all unused pins to tri-
state because doing otherwise might cause interference. To set all unused pins to tri-state, in the
Quartus II software, click Assignments > Device > Device and Pin Options > Unused Pins
and select an item from the Reserve all unused pins list.
Converting .sof Files to a .pof
To generate a programming file with different compression features, you must convert the .sof files to
a .pof .
24 Customizing and Generating IP Cores
UG-01082
2015.01.23
Altera Corporation Parallel Flash Loader IP Core User Guide
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