Development board setup, Setting up the board, Chapter 4. development board setup – Altera Stratix IV E FPGA User Manual
Page 17: Setting up the board –1
June 2011
Altera Corporation
Stratix IV E FPGA Development Kit User Guide
4. Development Board Setup
The instructions in this chapter explain how to set up the Stratix IV E FPGA
development board.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Stratix IV E FPGA development board ships with its board switches
preconfigured to support the design examples in the kit. If you suspect your board
might not be currently configured with the default settings, follow the instructions
in
“Factory Default Switch Settings” on page 4–2
to return the board to its factory
settings before proceeding.
2. The FPGA development board ships with design examples stored in the flash
memory device. Verify the PGM CONFIG SELECT rotary switch (SW5) is set to the
0 position to load the design stored in the factory portion of flash memory.
shows the switch location on the Stratix IV E FPGA development
board.
3. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J22) on the FPGA
board and plug the cord into a power outlet.
c
Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
4. Set the POWER switch (SW3) to the on position. When power is supplied to the
board, a blue LED (D21) illuminates indicating that the board has power.
The MAX II device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The PGM CONFIG SELECT rotary switch (SW5)
controls which design to load. When the switch is in the 0 position, the PFL loads the
design from the factory portion of flash memory. When the switch is in the 1 position,
the PFL loads the design from the user hardware portion of flash memory.
1
The kit includes a MAX II design which contains the MAX II PFL megafunction. The
design resides in the <install dir>\kits\stratixIVE_4se530_fpga\examples\max2
directory.
When configuration is complete, the CONF DONE LED (D22) illuminates, signaling
that the Stratix IV E device configured successfully.
f
For more information about the PFL megafunction, refer to
.