Altera Stratix IV E FPGA - Manual (Page 46)

6–20 Chapter 6: Board Test System
Using the Board Test System
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
Port
The Port control allows you to specify the type of test to run on the HSMC ports. The
following HSMC port tests are available:
■ HSMA x17 LVDS SERDES
■ HSMA x3 single-ended loopback
■ HSMB x17 LVDS SERDES
■ HSMB x3 single-ended loopback
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS —Selects pseudo-random bit sequences.
■ Memory —Selects a generic data pattern stored in the on chip memory of the
Stratix IV E device.
■ Math —Selects data generated from a simple math function within the FPGA
fabric.
Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
■ Detected errors —Displays the number of data errors detected in the hardware.
■ Inserted errors —Displays the number of errors inserted into the transmit data
stream.
■ Insert Error —Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.
Start
The Start control initiates HSMC transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.