Altera Stratix IV E FPGA - Manual (Page 30)

6–4 Chapter 6: Board Test System
Using the Board Test System
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
1 If you power up your board with the PGM CONFIG SELECT rotary switch (SW5) in a
position other than the 1 position, or if you load your own design into the FPGA with
the Quartus II Programmer, you receive a message prompting you to configure your
board with a valid Board Test System design. Refer to
“The Configure Menu” for
information about configuring your board.
Using the Board Test System
This section describes each control in the Board Test System application.
The Configure Menu
Use the Configure menu ( Figure 6–2 ) to select the design you want to use. Each design
example tests different functionality that corresponds to one or more application tabs.
To configure the FPGA with a test system design, perform the following steps:
1. On the Configure menu, click one of the following options to determine how to
pass data through the JTAG chain:
■ Use Fast Configuration —Compresses the data for faster loading.
■ Use Quartus II Programmer —Uses the standard JTAG-based configuration
method.
2. On the Configure menu, click the configure command that corresponds to the
functionality you wish to test.
3. In the dialog box that appears, click Configure or Download Start to download
the corresponding design’s SRAM Object File (.sof) to the FPGA. The download
process usually takes about a minute.
4. When configuration finishes, close the Quartus II Programmer, if using it. The
design begins running in the FPGA. The corresponding GUI application tabs that
interface with the design enable.
Figure 6–2. The Configure Menu