Altera Stratix IV E FPGA - Manual (Page 45)

Chapter 6: Board Test System 6–19
Using the Board Test System
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
The HSMC Tab
The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B
ports.
Figure 6–9 shows the HSMC tab.
1
You must have the loopback HSMC installed on the HSMC connector that you are
testing for this test to work correctly.
The following sections describe the controls on the HSMC tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Figure 6–9. The HSMC Tab