Altera Stratix IV GX FPGA Development Board - Manual (Page 20)

2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Table 2–7 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Stratix IV GX FPGA
Development Board, 530 Edition. The Stratix IV GX FPGA Development Board, 530
Edition supports three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ Flash memory download is used for configuring the FPGA using stored images
from the flash memory on either power-up or pressing the reset configuration
push-button switch (S1).
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
FPGA Programming over Embedded USB-Blaster
The USB-Blaster is implemented using a type-B USB connector (J7), a FTDI USB 2.0
PHY device (U39), and an Altera MAX II CPLD (U30). This allows the configuration
of the FPGA using a USB cable directly connected between the USB port on the board
(J7) and a USB port of a PC running the Quartus II software. The JTAG chain is
normally mastered by the embedded USB-Blaster found in the MAX
II CPLD
EPM2210 System Controller.
Table 2–7. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U30
IC - MAX II CPLD EPM2210
256FBGA -3 LF 1.8V VCCINT
Altera Corporation EPM2210GF256C3N www.altera.com