Altera Stratix IV GX FPGA Development Board - Manual (Page 23)

Chapter 2: Board Components 2–15
Configuration, Status, and Setup Elements
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
Table 2–8 shows the flash memory map storage.
Figure 2–5. PFL Configuration
MAX II CPLD
EPM2210 System Controller
FPGA_DATA [7:0]
FPGA_DCLK
FLASH_A [25:1]
FLASH_D [15:0]
DATA [7:0]
DCLK
INIT_DONE
nSTATUS
nCONFIG
CONF_DONE
MSEL0
MSEL1
MSEL2
MSEL3
2.5 V
10 k Ω
nCE
CFI Flash
CONF_DONE LED
10 k Ω
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [25:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RSTn
FLASH_ADVn
MSEL [3:0]
FPGA_nCONFIG
FPGA_CONF_DONE
FSM Bus Interface
FLASH_RYBSYn
Rotary Switch
PGM [2:0]
FPGA_nSTATUS
USB_DISABLEn
2.5 V
10 k Ω
125 MHz
2.5 V
FLASH_ADVn
RESET_CONFIGn
CONF_DONE_LED
2.5 V
10 k Ω
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RSTn
50 MHz
CONFIG_CLK
External JTAG Detect
Table 2–8. Flash Memory Map (Part 1 of 2)
Name Size (Kbyte) Address
Unused 128 0x03FE0000 – 0x03FFFFFF
User Software 11,797 0x034A0000 – 0x03FDFFFF
User Hardware 21,627 0x02000000 – 0x0349FFFF
zipfs—HTML, Web Content 5,898 0x01A60000 – 0x01FFFFFF
Factory Software 5,898 0x014C0000 – 0x01A5FFFF
Factory Hardware 21,627 0x00020000 – 0x014BFFFF
PFL Option Bits 32 0x00018000 – 0x0001FFFF