Altera Stratix IV GX FPGA Development Board - Manual (Page 59)

Chapter 2: Board Components 2–51
Memory
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
Table 2–47 lists the DDR3 component reference and manufacturing information.
U18.A3 Data bus byte lane 5 DDR3BOT_DQ47
1.5-V SSTL Class I
AT17
U18.D3 Write mask byte lane 5 DDR3BOT_DM5 AN18
U18.C7 Data strobe P byte lane 5 DDR3BOT_DQS_P5 AU17
U18.B7 Data strobe N byte lane 5 DDR3BOT_DQS_N5 AV17
U24.E3 Data bus byte lane 6 DDR3BOT_DQ48 AV26
U24.F7 Data bus byte lane 6 DDR3BOT_DQ49 AU25
U24.F2 Data bus byte lane 6 DDR3BOT_DQ50 AT25
U24.F8 Data bus byte lane 6 DDR3BOT_DQ51 AN25
U24.H3 Data bus byte lane 6 DDR3BOT_DQ52 AR25
U24.H8 Data bus byte lane 6 DDR3BOT_DQ53 AP24
U24.G2 Data bus byte lane 6 DDR3BOT_DQ54 AP25
U24.H7 Data bus byte lane 6 DDR3BOT_DQ55 AW26
U24.E7 Write mask byte lane 6 DDR3BOT_DM6 AN24
U24.F3 Data strobe P byte lane 6 DDR3BOT_DQS_P6 AT26
U24.G3 Data strobe N byte lane 6 DDR3BOT_DQS_N6 AU26
U24.D7 Data bus byte lane 7 DDR3BOT_DQ56 AJ23
U24.C3 Data bus byte lane 7 DDR3BOT_DQ57 AK24
U24.C8 Data bus byte lane 7 DDR3BOT_DQ58 AF23
U24.C2 Data bus byte lane 7 DDR3BOT_DQ59 AH23
U24.A7 Data bus byte lane 7 DDR3BOT_DQ60 AG22
U24.A2 Data bus byte lane 7 DDR3BOT_DQ61 AJ22
U24.B8 Data bus byte lane 7 DDR3BOT_DQ62 AH22
U24.A3 Data bus byte lane 7 DDR3BOT_DQ63 AE22
U24.D3 Write mask byte lane 7 DDR3BOT_DM7 AF22
U24.C7 Data strobe P byte lane 7 DDR3BOT_DQS_P7 AK23
U24.B7 Data strobe N byte lane 7 DDR3BOT_DQS_N7 AL23
Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board Reference Description Schematic Signal
Name
I/O Standard
Stratix IV GX
Device
Pin Number
Table 2–47. DDR3 Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U5, U12, U18, U24 8 M × 16-bit × 8 banks, 667M, CL9 Micron MT41J64M16LA-15E www.micron.com