Altera Arria GX Development Board - Manual (Page 19)

Altera Corporation Reference Manual 2–9
October 2007 Arria GX Development Board
Board Components
f
Two single-pole, double throw switches are used to select JTAG chain
options, refer to
“JTAG Chain Configuration” on page 2–9 for more
information.
JTAG Chain Configuration
The simplest way to configure the Arria GX device is with the JTAG
configuration scheme. The JTAG configuration scheme requires just the
USB-Blaster
™ cable and the Quartus ® II Software.
To setup JTAG configuration, connect one end of the USB-Blaster cable to
the computer’s USB port and the other end to the 10-pin JTAG header on
the board. To download a design file to the Arria GX device, use the
Quartus II Programmer.
f
For information on the Quartus II Programmer, refer to Quartus II
Development Software Handbook.
The board’s JTAG chain is connected to the Arria GX device and
optionally the MAX II CPLD, as well as the HSMC expansion connector.
The MAX II and HSMC slots are by-passable so that devices on the
mezzanine card can be optionally addressed through JTAG.
1
The MAX II device and HSMC interface can be by-passed or
chained together via board references SW2 and SW3
respectively.
To configure the Arria GX device, you must perform the following steps:
1. Set up a new JTAG chain (including both the MAX II CPLD and the
Arria GX device)
RSU with FPP
decompression 1 1 0 0 1 1
JTAG (3) N/A N/A N/A N/A N/A N/A
Notes to Table 2–4 :
(1) The MSEL bits are auto-generated by the MAX II device’s configuration design.
(2) Remote system upgrade uses FPGA PGM [2:0] outputs page select pins.
(3) JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings are
ignored.
Table 2–4. Supported Configuration Modes & Settings, Note (1)
Configuration
Scheme
FPGA MSEL Settings (from MAX II Device) DIP Switch Settings
MSEL-3 MSEL-2 MSEL-1 MSEL-0 CFG_MODE-1 CFG_MODE-0