Altera Arria GX Development Board - Manual (Page 26)

2–16 Reference Manual Altera Corporation
Arria GX Development Board October 2007
Clocking Circuitry
Figure 2–6. Oscillator Clocking Diagram
Table 2–12 lists the board’s clock distribution system.
3-4
3-4

#LOCK
,644,
,6$3 ,6$3 ,6$3 ,6$3
,6$3
,6$3
3-!
2
4
4EST
/3#
,6$3
4RANSLATOR
&ROM
$#
!#
!#
!
#
!RRIA
2EFCLK
)NPUT
-!8
#ONFIGURATION
#ONTROLLER
!RRIA
%NHANCED
)NPUTS
Table 2–12. Arria GX Development Board Clock Distribution (Part 1 of 2)
Source
Schematic
Signal Name
I/O Standard
Arria GX Pin
Number
MAX II Pin
Number
100 MHz (X1) oscillator or
SMA clock input (J4)
(1)
CLK1_P Not terminated
LVDS U28
CLK1_N U27
CLK2_P (2) LVDS
CLK2_N (2)
100M_REFCLK_P Not terminated
LVDS AB4
100M_REFCLK_N AB5
CLK2 3.3 V AC15
MAXII_CLK_IN 3.3 V E1
62.5 MHz oscillator (X3) HSMA_REFCLK2_P LVDS G4
HSMA_REFCLK2_N G5