Altera Arria GX Development Board - Manual (Page 7)

Altera Corporation Reference Manual 1–1
October 2007 Preliminary
1. Overview
Introduction This document describes the hardware features of the Arria ™ GX
development board, including detailed pinout information to enable
designers to create custom FPGA designs that interface with all
components of the board.
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For information on setting up and powering up the Arria GX
development board and using the kit’s demo software, please refer to the
Arria GX Development Kit Getting Started User Guide.
General
Description The Arria GX development board provides a hardware platform for
developing and prototyping high-performance PCI Express (PCIe)-based
designs as well as to demonstrate the Arria GX device’s embedded
transceiver and memory interface circuitry.
With up to 8-integrated transceiver channels and support for high-speed,
low latency memory access via a DDR2 SDRAM memory interface, the
Arria GX development board provides a fully-integrated solution for
multi-channel, high-performance applications, while also using limited
board space.
The Arria GX transceivers are optimized for endpoint and bridging
applications. Through the use of Altera
® MegaCore ® functions (or other
intellectual property [IP] cores) and expansion connectors, you can enable
the inter-operability of the Arria GX device’s transceivers with
third-party application specific semiconductor products (ASSP) for either
point-to-point switching or bridging applications.
To simplify the design process, Altera provides a PCIe reference design—
available from the Altera website—for use as either a design starting
point or as an experimental platform. The PCIe reference design has been
verified by Altera engineers and is distributed with the Arria GX
Development Kit (ordering code: DK-DEV-1AGX60N).
1 The Arria GX development board is a PCI-Special Interest
Group (SIG) compliant board.